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Global Mixed-mode Technology Inc.
G569C
CD-RW Laser Diode Current Driver
Features
Single +5V supply Laser diode read current driver Laser diode write current driver Laser diode Erase current driver Deltap circuit to control write current FSA circuit to integrate photo diode current Cagain circuit to convert Vcagain into current Dalpha circuit to perform voltage subtraction and limiting 3-wire interface to control internal DAC A build-in OP-AMP 48-pin SSOP package
General Description
The G569C is a single chip solution for the various functions relating to laser diode operation in a CD-RW drive. The G569C integrates nine functional blocks in one chip. It has five voltage-to-current converters, one current-to-voltage converters which is called FSA, one OP-AMP, one eight-channels D/A converter, and one voltage subtracter with output clamping capability called Dalpha. Three of the five V-to-I converters provide the laser diode currents for Read, Write, and Erase operations, respectively; another one of the V-I converters provides the Cagain current; and the other one provides Deltap current which can selectively shunt a certain amount of laser diode current for write operation. For the Write and Erase operations, the voltage to current conversion ratio can be adjusted using an external or internal DAC resistor array. The FSA circuit performs integration on the output current of an external photo diode, and sample-and-hold the peak voltage. It is used to monitor the laser diode power. The internal eight-channel D/A converter is used to provide the input voltage for above functional blocks. The G569C is available in a 48-pin SSOP surface-mount package.
Applications
CD-RW Drive
Pin configuration
G569C
IW_IN LS_DELTA TST1 PWO DALPHA PWO_I PWB PWMAX PWMIN /RESET VSS EDB LS_ERASE PERASE RECORD CDR S2V9 CAGAIN2 CAGS_I DCAGAIN CAGAIN RCAGAIN1 RCAGAIN2 PRFINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 WDB LS_WRITE PWRITE LD DI CLK VSS VOUT VIVI+ VDD FSOF FSWS FSCLR FSW IFSA FSR FSRS VDD SELN4_IN PR_I LS_READ IR PRCOARSE
Ordering Information
ORDER ORDER NUMBER NUMBER (Pb free)
G569CS8U G569CS8Uf Note: S8: SSOP-48 U: Tape & Reel
TEMP. RANGE
0C to 85C
PACKAGE
SSOP-48
SSOP-48
Ver: 1.0 Oct 02, 2000
TEL: 886-3-5788833 http://www.gmt.com.tw
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Global Mixed-mode Technology Inc.
Absolute Maximum Ratings
VCC to GND..........................................-0.3V to +6V Dalpha to GND........................................-3V to +6V All other pin to GND..............................-0.3V to +6V ESD protetion (human body model)..................2000V Continuous power dissipation (TA=70C),
G569C
derate .7mW/C about 70C)......................... 695mW Operating Temperature Range..........-10C to +100C Junction Temperature..................................+150C Storage temperature Range..............-65C to +165C Reflow Temperature (soldering, 10sec)...........+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
PARAMETER
Supply voltage High-level input voltage Low-level input voltage Operating free-air temperature
SYMBOL
VDD VIH VIL TA
MIN
4.75 2 0
TYP
5
MAX
5.5 0.8 70
UNITS
V V V C
Electrical Characteristics (VCC = 5V, TA = 0C to +70C, unless otherwise noted)
PARAMETER
Supply voltage range PWO output voltage Dalpha input voltage PWO_I input voltage PWB output voltage PWMAX output voltage PWMIN output voltage IE output current S2V9 input voltage Cagain output current PRFine output voltage PRCoarse output voltage IR output current PR_I input voltage FSR output voltage FSW output voltage VI- input voltage VI+ input voltage IW output current Operation current VS2V9 0 0 0 0 0 0 0 0 0 0 41
CONDITIONS
MIN
4.75 0 -3.0 0 0 0 0 0
TYP
5.0
MAX
5.5 VS2V9 3.5 1.5 VS2V9 VS2V9 VS2V9 130
UNITS
V V V V V V V mA V mA V V mA V V V V V mA mA
2.9 1.2 VS2V9 VS2V9 160 2.16 3.0 3.0 3.5 3.5 160
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Global Mixed-mode Technology Inc.
Pin Description
PIN NO. PIN NAME I/O
1 2 3 4 5 6 7 8 9 10 11,42 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30,38 31 32 33 34 35 36 37 IW_IN LS_DELTA TST1 PWO DALPHA PWO_I PWB PWMAX PWMIN /RESET VSS EDB LS_ERASE PERASE RECORD CDR S2V9 CAGAIN2 CAGS_I DCAGAIN CAGAIN RCAGAIN1 RCAGAIN2 PRFINE PRCOARSE IR LS_READ PR_I SELN4_IN VDD FSRS FSR IFSA FSW FSCLR FSWS FSOF I O I O I I O O O I I O I O I I I O I O O O O O O O I I I I I O I O O I I
G569C
PIN FUNCTION
A diode of type BAS216 should be connected between this pin and node IW. This pin provides the path for sinking IW current. Connect a 10 resistor from this pin to VSS Test pin. Connect to ground for normal operation. DAC output, connect to PWO_I through a resistor divider Control voltage input Control voltage input Voltage output Voltage output Voltage output Logic input. A Low on this pin reset all DAC latches to 0. Ground pin Connect to the base node of external PNP BJT (Type BC808). Connect a 6.8 (1206 type) resistor from this pin to VDD Connect a DAC resistor array from this pin to VSS Logic input, a high indicates in recording mode. Logic input, a high indicates in CD-R mode. Voltage input. Contribute to current output on CAGAIN pin and provides internal DAC reference voltage. Tristate output. Connect 62K to pin CAGAIN. Logic input, 0~2V swing. An optional resistor may be added to modify the output current on CAGAIN Current output A 16.2K resistor should be connected from this pin to VSS A 3.9K resistor should be connected from this pin to VSS DAC output, connect to PR_I through a resistor divider DAC output, connect to PR_I through a resistor divider Read current output for laser diode Connect two 22 (1206 type) resistors from this pin to VDD Voltage input which controls the current on IR pin Logic input. This pin can be shorted to pin CDR or be connected to the voltage divider formed by CDR and SELN4. Supply voltage input. Each VDD pin should have a 0.1F bypass capacitor to VSS. Logic input, when FSRS=1, the voltage on pin FSCLR is sampled onto pin FSR, else FSR is in hold mode. Sampled voltage output, controlled by FSRS If internal integration control circuitry is used, connect a photo diode from this pin to +30V. connect it to VDD otherwise Sampled voltage output, controlled by FSWS Sampling capacitors and resistor are connected to this pin. Logic input, when FSWS=1, the voltage on pin FSCLR is sampled onto pin FSW, else FSW is in hold mode. If internal integration control circuitry is used, connect the control signal to this pin. A logic low enable the current charging on the capacitors on pin FSCLR with the current from IFSA. Connect this pin to VDD if internal integration control circuitry is not used. Non-inverting input of Op Amp Inverting input of Op Amp Op Amp output Clock input of I2S bus Data input of I2S bus Latch data input of I2S bus Connect a DAC resistor network from this pin to VSS Connect a 6.8 (1206type) from this pin to VDD Connect to the base node of external PNP BJT. (Type BC807-40)
39 40 41 43 44 45 46 47 48
VI+ VIVOUT CLK DI LD PWRITE LS_WRITE WDB
I I O I I I O I O
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Global Mixed-mode Technology Inc.
Detail Description The typical application circuit of G569C is shown in Fig. 1. The block diagram of G569C is shown in Fig. 2. It contains nine circuit blocks. The operation of these blocks is described below. READ Block This block is equivalent to an operational transconductance amplifier (OTA). The voltage on PR_I pin is the input voltage, VPR_I; the output current, IR, is delivered on pin IR. The relationship between VPR_I and IR is given by: IR = 820 x VPR_I /( R232 R233) where IR is in mA, VPR_I is in volt, and R is in . The recommended values for R232 and R233 are 22, the maximum VPR_I is 2.16 V, thus the maximum IR is 160mA. Since IR must flow through the two external 22 resistors connected between VDD and LS_READ pin, type 1206 SMD resistors must be used to handle the power dissipation. ERASE Block This block is also equivalent to an operational transconductance amplifier (OTA). The voltage on PWD node is the input voltage, VPWD; the output voltage, VEDB, can be used to drive an external PNP BJT to provides desired IE current. The relationship between VPWD and IE is given by: IE = 1800 x VPWD / RPERASE, R235
G569C
programming of the OTA's transconductance. An internal DAC can be enabled through I2S bus to replace the external DAC resistor array. The maximum RPWRITE is 7.5K. The maximum IW is 130 mA. Since IW must flow through the external 6.8 resistors connected between VDD and LS_WRITE pin, type 1206 SMD resistors must be used to handle the power dissipation. DELTAP Block This block is a current sink used to selectively sink the IW current. When DP4 is low, the current sink reduces the output current on IW by the amount of the magnitude of the current sink. The magnitude of the current sink, Is, is given by: Is = 3 20 x VDELTAP / RLS_DELTA,
where Is is in mA; VDELTAP, in volt, is an internal DAC output; and RLS_DELTA, in K, is the resistance from pin LS_DELTA to ground. Type 1206 SMD resistors must be used for RLS_DELTA to handle the power dissipation. When DP4 is high, the current output on IW current is not affected. DALPHA Block The function of this block is a voltage subtracter. The voltage on pin PWB, VPWB, is given by: VPWB = 2 x VPWO_I - VDALPHA,
where IE is in mA, VPWD is in volt, and RPERASE, in K, is the total resistance from pin PEARSE to ground. Typically, a digital-to-analog converter (DAC) resistor array is connected at PERASE pin to allow digital programming of the OTA's transconductance. The maximum RPERASE is 7.5K. An internal DAC can be enabled through I2S bus to replace the external DAC resistor array. The maximum IE is 130 mA. Since IE must flow through the external 6.8 resistors connected between VDD and LS_ERASE pin, type 1206 SMD resistors must be used to handle the power dissipation. WRITE Block This block is also an operational transconductance amplifier (OTA). The voltage on PWD node is the input voltage, VPWD; the output voltage, VWDB, can be used to drive an external PNP BJT to provides desired IW current. The relationship between VPWD and IW is given by: IW = 1800 x VPWD / RPWRITE, R234
where VPWO_I and VDALPHA are the voltages on pins PWO_I and DALPHA, respectively. In addition, the magnitude of the output voltage VPWB is limited by VPWMAX and VPWMIN, which are the voltages on pins PWMAX and PWMIN. When 2xVPWO_I - VDALPHA < VPWMIN, then VPWB = VPWMIN. When 2xVPWO_I - VDALPHA, > VPWMAX, then VPWB = VPWMAX. The input voltage ranges of VPWMAX and VPWMIN are 0 to VS2V9 which is the voltage input at S2V9 pin, and the condition VPWMAX > VPWMIN must hold. Note that the input voltage range of VDALPHA is -3V to +3.5V. CAGAIN Block This block is also an operational transconductance amplifier (OTA). The voltage on VCAGAIN pin is the input voltage, VVCAGAIN; the output current, ICAGAIN, is delivered on pin CAGAIN. Let the voltages on pins CDR, CAGS, CAGAIN and S2V9 be denoted as VCDR, VCAGS, VCAGAIN, VS2V9, respectively. The relationship between VVCAGAIN and ICAGAIN is given by: When VCDR = 5V, VCAGS = 5V ICAGAIN = 1.2 x VCAGAIN / (R108 R109) + (VS2V9 VCAGAIN) / R195, When VCDR = 5V, VCAGS = 0V ICAGAIN = (VS2V9 - VCAGAIN) / R195
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where IW is in mA, VPWD is in volt, and RPWRITE, in K is the total resistance from pin PWRITE to ground. Typically, a digital-to-analog converter (DAC) resistor array is connected at PWRITE pin to allow digital
Ver: 1.0 Oct 02, 2000
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Global Mixed-mode Technology Inc.
When VCDR = 0V, VCAGS = 5V, VRECORD = 0V ICAGAIN = 1.2 x VCAGAIN / R108 + (VS2V9 - VCAGAIN) / R195, When VCDR = 0V, VCAGS = 5V, VRECORD = 5V ICAGAIN = 1.2 x VCAGAIN / R108 When VCDR = 0V, VCAGS = 0V, VRECORD = 0V ICAGAIN = (VS2V9 - VCAGAIN) / R195, When VCDR = 0V, VCAGS = 0V, VRECORD = 5V ICAGAIN = 0 mA, Where ICAGAIN is in mA; all voltages are in volt, and all resistance are in K. FSA Block The FSOF/FSON control the integration of the photodiode current, IFSA, on the capacitors connected on pin FSCLR to obtain a voltage. The voltage on FSCLR pin is connected to two sample-and-hold circuit. The voltages sampled by the control voltage on FSWS and FSRS pins are output on FSW and FSR pins, respectively. Namely, When VFSWS = 5V, VFSW = VFSCLR, When VFSWS = 0V, VFSW = the previously sampled value; When VFSRS = 5V, VFSR = VFSCLR, When VFSRS = 0V, VFSR = the previously sampled value. The charging of FSCLR node is controlled by signals VFSOF and VFSON.
G569C
When VFSOF = 0V, the FSCLR pin is charged by IFSA. When VFSOF = 5V, the FSCLR pin is not charged by IFSA. The FSCLR, RDGAIN1, RDGAIN2, and RDGAIN3 pins are driven by an open-drain buffer, i.e., the voltages on these pins are either 0V or Hi-Z. The capacitance values of the three capacitors connecting to the FSCLR may need to be changed if loader other than CDL4800 is used. When VFSCLR = 0V, the charges on the capacitors are discharged to 0V. When VFSCLR = Hi-Z, the charging of FSCLR node is allowed. When VRDGAIN1 = 0V, the VFSCLR is given by: VFSCLR = IFSA x R187. When VRDGAIN1 = Hi-Z, the charging of FSCLR node is allowed. When VRDGAIN2 = 0V, the capacitor C123 is in parallel with C116. When VRDGAIN2 = Hi-Z, the capacitor C123 has no effect. When VRDGAIN3 = 0V, the capacitor C117 is in parallel with C116. When VRDGAIN3 = Hi-Z, the capacitor C117 has no effect.
Ver: 1.0 Oct 02, 2000
TEL: 886-3-5788833 http://www.gmt.com.tw
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Global Mixed-mode Technology Inc.
G569C
5V IFSA R71 100 BF824 820 5V R69 100 R68 FSON
FSOF 5V CAGAIN R195 62K R108 16.2K R109 3.9K CDR SELN4 CAGS R67 CAGS_I (pin 19) 330 R66 220 C113 330pF R230 4.7K R231 150K R229 6.8K 5V BC847B R232 (1206) IR 5V R235 6.8 (1206) 12V R226 1.5K IR (pin 26) LS_DELTA (pin 2) R236 10 (1206) R236 R92 220 BC808 IE R96 1M FSOF (pin 37) VSS (pin 11,42) R211 47 C135 100nF EDB (pin 12) PERASE (pin 14) PWO (pin 4) 150K PWO_I (pin 6) R127 150K 5V 22 22 R232 (1206) LS_READ (pin 27) TST1 (pin 3) PWRITE (pin 46) PRCOARSE (pin 25) PRFINE (pin 24) PR_I (pin 28) WDB (pin 48) 47 IW_IN (pin 1) R210 R234 (1206) 5V 100K 10K CAGAIN (pin 21) CAGAIN2 (pin 18) RCAGAIN1 (pin 22) RCAGAIN2 (pin 23) CDR (pin 16) SELN4_IN (pin 29) C116 560pF IFSA (pin 33) FSCLR (pin 35) VDD (pin 30,38) 0.1F 30V
R70 820
R187 22K
VRDGAIN1 FSCLR(pin 35)
C123 2.2nF
C117 1.5nF
VRDGAIN3 VRDGAIN2
12V 6.8 LS_WRITE (pin 47) R302 2.2K
R191 220
C127 100nF
BC807_40 IW
BAS216 R192 330 R124 270
5V
DP4
C52 68pF R36 1M
LS_ERASE (pin 13)
C53 1nF FSOF
Fig 1. Typical application circuit Note: The circuits in the dotted-line are the suggested circuit when internal integration circuit is not used. Please refer to pin description for details.
Ver: 1.0 Oct 02, 2000
TEL: 886-3-5788833 http://www.gmt.com.tw
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Ver: 1.0 Oct 02, 2000
S2V9 (pin 17) PWB (pin 7) (pin 5) DALPHA PWO_I
(pin 10)
/RESET
CLK
(pin 43)
DI (pin 6)
(pin 44)
DALPHA
(pin 45)
LD
(pin 12)
EDB
LS_ERASE REF CH 5 OUT
(pin 13)
ERASE D/A
(pin 14) REF CH 4 OUT REF CH 6 OUT REF CH 1 OUT REF CH 2 OUT REF CH 3 OUT REF CH 8 OUT REF CH 7 OUT PWD VDELTAP
(pin 8) PWMAX (pin 9) PWMIN (pin 4) (pin 25) (pin 24) PRFINE PWO PRCOARSE
PERASE
Internal DAC Resistor Array (CH10)
(pin 46)
PWRITE
Internal DAC Resistor Array (CH9)
(pin 34) FSW (pin 32) (pin 33) FSR IFSA (pin 35)
Global Mixed-mode Technology Inc.
Fig 2. Block Diagram of G569C
7
VCAGAIN
LS_WRITE
(pin 47)
(pin 48)
WDB
WRITE
IW_IN
(pin 1)
FSA
FSCLR (pin 37) (pin 36) (pin 31) FSRS FSOF FSWS
TST1
(pin 3)
(pin 2)
DELTAP
LS_DELTA
(pin 20)
DCAGAIN
(pin 22)
RCAGAIN1
CAGAIN
(pin 39) VI+
RCAGAIN2
(pin 23)
(pin 18)
CAGAIN2
SELN4_IN
(pin 29)
READ
(pin 40) VI-
G569C
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CDR (pin 16) RECORD (pin 15)
CAGS_I (pin 19)
CAGAIN (pin 21)
PR_I (pin 28)
LS_READ (pin 27)
IR (pin 26)
VOUT (pin 41)
Global Mixed-mode Technology Inc.
Internal DAC Digital Format
12BIT SERIAL DATA 1
DATA D11
G569C
9
D3
2
D10
3
D9
4
D8
5
D7
6
D6
7
D5
8
D4
10
D2
11
D1
(LSB) 12
D0
CLK
Data Assignment
D0 (LSB) D8 (MSB) D9 D10 D11 (LSB) D1 D2 D3 D4 D5 (MSB) : DAC SELECT DATA D6 D7 : DAC DATA
DAC Select Data
D8
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D9
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
D10
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D11
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don't Care PRCOARSE Selection PRFINE Selection VCAGAIN Selection PWMIN Selection PWMAX Selection PWO Selection DELTAP Selection PWD Selection WRITE Selection ERASE Selection Don't Care Don't Care Don't Care Don't Care Don't Care
DAC Selection
Digital Data Format for Internal DAC
D0
0 1 0 1 | 1
D1
0 0 1 1 | 1
D2
0 0 0 0 | 1
D3
0 0 0 0 | 1
D4
0 0 0 0 | 1
D5
0 0 0 0 | 1
D6
0 0 0 0 | 1
D7
0 0 0 0 | 1
DAC Output
0 VIN / 256 x 1 VIN / 256 x 2 VIN / 256 x 3 | VIN / 256 x 255
Digital Data Format for WRITE and ERASE
D0
0 1
D1
x 0/1
D2
x 0/1
D3
x 0/1
D4
x 0/1
D5
x 0/1
D6
x 0/1
D7
x 0/1
Comments
Disable Internal R2R Network Enable Internal R2R Network D1 is LSB , D7 is MSB
Ver: 1.0 Oct 02, 2000
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Global Mixed-mode Technology Inc.
Timing Chart
R DI
G569C
LSB
MSB D11 D10 D9
D0
CLK LD
VO
*Input data carried out LD signal Low besides CLK signal positive edge. CLK, LD is keep generally HIGH level.
AC Characteristics
Symbol
tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDo tLDD
Parameter
Clock "L" Pulse Width Clock "H" Pulse Width Clock Rise Time Clock Fall Time Data Set Up Time Data Hold Time LD Set Up Time LD Hold Time LD "H" Pulse Duration Time Data Output Delay Time D-A Output Setting Time
Measurement Condition
200 200
Limit
Unit
nS nS 200 nS nS nS nS nS nS 350 300 nS S
60 100 200 100 100 CL=100pF CL 100pF,VAO:0.1< = > 2.6V This Time Until The Output Becomes The final Value Of 1/2 LSB 70
Timing Chart
t CR t CKH t CF
CLK t CKL
t LDC DI t DCH t CHD t CHL LD t LDD t LDH
D-A OUTPUT t Do Do OUTPUT
Ver: 1.0 Oct 02, 2000
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Global Mixed-mode Technology Inc.
Package Information
C
G569C
L
E1 E
h x 45
D
A 0.004 C SEATING PLANE e b A1
SYMBOL
A A1 b c D e E E1 h L
MIN.
2.413 0.203 0.203 0.127 15.75 10.033 7.391 0.381 0.508 0
DIMENSION IN MM NOM.
2.591 0.305
MAX.
2.794 0.406 0.343 0.254 16.00 10.668 7.595 0.635 1.016
MIN.
0.095 0.008 0.008 0.005 0.620 0.395 0.291 0.015 1.020 0
DIMENSION IN INCH NOM.
0.102 0.012
MAX.
0.110 0.016 0.0135 0.010 0.630 0.420 0.289 0.025 0.040
15.88 0.635 BASIC 7.493
0.625 0.025 BASIC 0.295
Ver: 1.0 Oct 02, 2000
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Global Mixed-mode Technology Inc.
Package Description: SSOP-48
Quantity /Reel Reel Diameter Carrier Tape (Width) Carrier Tape (Pitch) : : : : 1000 / Reel 13" 32mm 16mm
G569C
Mechanical Polarization
Top View Shown With Cover Tape Removed EIA-JEDEC SO Package Outline Style
Termination No.1
User Direction of Feed
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
Ver: 1.0 Oct 02, 2000
TEL: 886-3-5788833 http://www.gmt.com.tw
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